MODES (DSP, Digital and Two Channel)
DSP Processing Essentials
Prior to discussing the difference between modes, it’s important to cover two common methods of creating DSP within a Receiver or Processor/Pre-Amp. One method implements a SHARC (Super Harvard Architecture) based processor, as found in the Sony STR-DA5ES and the TA-E9000ES. Another uses RISC (Reduced Instruction Set Computer) Processors as that found in the STR-DA4ES and STR-DA7ES. Many HiFi Enthusiasts believe SHARC Processors are superior to RISC. To debate this issue is beyond the scope of this article. Provided instead, is information on how the differences apply to the units within this article.
DSP Processing for the Sony TA-E9000ES
At the heart of the Sony TA-E9000ES DSP Board are three separate 32-Bit Digital Signal Processor IC’s. The multi-channel digital and audio decoding is done by an Analog Devices SHARC KS-160, 32-bit floating point DSP Chip. This processor uses “Super” Harvard Architecture to enable all variety of real-time embedded applications. The unique memory architecture consisting of two large, on-chip, dual-ported SRAM blocks, coupled with a sophisticated I/O processor, gives the SHARC the bandwidth for sustained high-speed computations. This allow the SHARC Processor to provide parallel-processing all within a single unit. Please note that a SHARC Processor was also used in the STR-DA5ES, but information on this unit is not within the context of this article.
DSP Processing for the Sony STR-DA4ES
At the heart of the Sony STR-DA4ES and STR-DA7ES DSP Board are three RISC Processors. RISC Processors are arithmetic-logic units that use a minimal instruction set, emphasizing the instructions used most often, and optimizing them for the fastest possible execution. Software for RISC processors must handle more operations than traditional CISC [Complex Instruction Set Computer] processors, but RISC processors have advantages in applications that benefit from faster instruction execution, such as engineering and graphics workstations and parallel-processing systems. Parallel-processing is the necessary method of creating DSP Modes in any Receiver or Processor/Pre-Amp. Unlike SHARC, where parallel-processing takes place in a single unit, RISC requires two or more interconnected processors, each of which executes a portion of the task. In the STR-DA4ES and 7ES, Sony uses three RISC Processors to implement these tasks. Two of them (labeled as LHC and 2nd RHC) are the Toshiba TC927 (no information available). The other (labeled as 1st RHC) is totally unidentifiable as it is on the bottom of the board. These processors access data through shared memory. The efficiency of parallel-processing is dependent upon the development of programming languages that optimize the division of the tasks among the processors.
In general, RISC Processors tend to be less costly to design, test, and manufacture then SHARC and CISC Processors. In the mid-1990s RISC processors began to be used in personal computers instead of the CISC processors that were used since the introduction of the microprocessor. RISC Processors are also used in applications such as Cell Phones and other, commercial microprocessor based products.
For more information on RISC and SHARC Processing, feel free to review the following sites:
http://www.analog.com/library/dspManuals/32BitIndex.html
http://www.analog.com/technology/dsp/developmentTools/pdf/select_guide.pdf
http://www.analog.com/technology/dsp/Sharc/index.html
http://www.infoplease.com/ce6/sci/A0841981.html
